求个用vhdl实现8-3编码器，在线等啊，急！

library ieee;
use ieee.std_logic_1164.all;
entity yimaqi is
port(clk，clr:in std_logic;
d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(2 downto 0));
end yimaqi;
architecture y of yimaqi is
begin
process(d)
begin
case d is
when"01111111"=>q<="000";
when"10111111"=>q<="001";
when"11011111"=>q<="010";
when"11101111"=>q<="011";
when"11110111"=>q<="100";
when"11111011"=>q<="101";
when"11111101"=>q<="110";
when"11111110"=>q<="111"; when others=>q<="111";
end case;
end process;
end y;