急求eda课程设计一份:脉冲信号发生器的设计

给个时钟信号发生器参考一下吧
一个电子系统中需要三种时钟，分别是：1000HZ、100Hz、50Hz，系统输入时钟为100KHz。SYVHDL描述该时钟发生器。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
generic(count_value:integer:=9);
port(clk:in std_logic;
co:out std_logic);
end counter;
architecture a of counter is
signal cnt:integer range 0 to count_value;
begin
process(clk)
begin
if(clk'event and clk='1')then
if(cnt=count_value)then
cnt<=0;
co<='1';
else
cnt<=cnt+1;
co<='0';
end if;
end if;
end process;
end a;
（2）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div3 is
port (clk:in std_logic;
fout:out std_logic_vector(2 downto 0));
end div3;
architecture a of div3 is
signal co_clk:std_logic_vector(3 downto 0);
component counter is
generic(count_value:integer:=9);
port(clk:in std_logic;
co:out std_logic);
end component;
begin
cnt0:counter
generic map(count_value=>9)
port map(clk=>clk， co=>co_clk(3));
cnt1:counter
generic map(count_value=>9)
port map(clk=>co_clk(3)， co=>co_clk(2));
cnt2:counter
generic map(count_value=>9)
port map(clk=>co_clk(2)， co=>co_clk(1));
cnt3:counter
generic map(count_value=>1)
port map(clk=>co_clk(1)， co=>co_clk(0));
fout(2)<=co_clk(2);
fout(1)<=co_clk(1);
fout(0)<=co_clk(0);
end a;