如何用VHDL设计一分钟的计时器(带毫秒显示)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CLOCK IS
PORT( CLK: IN STD_LOGIC;
DOUT1:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0); -----秒钟个位输出
DOUT2:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0); -----秒钟时位输出
DOUT3:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0); -----分钟个位输出
DOUT4:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0); -----分钟时位输出
DOUT5:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0); -----时钟个位输出
DOUT6: BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0); -----时钟十位输出
CO: OUT STD_LOGIC);

-- LED1: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
-- LED2: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
-- LED3: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
-- LED4: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
-- LED5: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0);
-- LED6: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0));
END CLOCK;

ARCHITECTURE CK OF CLOCK IS
SIGNAL CO1: STD_LOGIC;
SIGNAL CO2: STD_LOGIC;
SIGNAL QOUT1: STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL QOUT2: STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL QOUT3: STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL QOUT4: STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL QOUT5: STD_LOGIC_VECTOR( 3 DOWNTO 0);
SIGNAL QOUT6: STD_LOGIC_VECTOR( 3 DOWNTO 0);

-- COMPONENT LED IS
-- PORT( QIN: STD_LOGIC_VECTOR(3 DOWNTO 0);
-- QOUT: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0));
-- END COMPONENT;
BEGIN
U1: PROCESS( CLK ) ---秒钟进程表
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF QOUT1 = 9 THEN
IF QOUT2=5 THEN
CO1 <= '1';
QOUT1 <="0000";
QOUT2 <="0000";
ELSE
QOUT1 <= "0000";
CO1 <='0';
QOUT2 <= QOUT2+1;
END IF;
ELSE
QOUT1 <= QOUT1+1;
CO1 <= '0';
END IF;
END IF;
END PROCESS;
DOUT1 <= QOUT1;
DOUT2 <= QOUT2;

U2: PROCESS(CO1) --分钟进程表
BEGIN
IF CO1'EVENT AND CO1='1' THEN
IF QOUT3 = 9 THEN
IF QOUT4=5 THEN
CO2 <= '1';
QOUT3 <="0000";
QOUT4 <="0000";
ELSE
QOUT3 <= "0000";
CO2 <='0';
QOUT4 <= QOUT4+1;
END IF;
ELSE
QOUT3 <= QOUT3+1;
CO2 <= '0';
END IF;
END IF;
END PROCESS;
DOUT3 <= QOUT3;
DOUT4 <= QOUT4;

U3: PROCESS(CO2) --分钟进程表
BEGIN
IF CO2'EVENT AND CO2='1' THEN
IF QOUT5 = 3 THEN
IF QOUT6=2 THEN
CO <= '1';
QOUT5 <="0000";
QOUT6 <="0000";
ELSE
QOUT5 <= "0000";
CO <='0';
QOUT6 <= QOUT6+1;
END IF;
ELSE
QOUT5 <= QOUT5+1;
CO <= '0';
END IF;
END IF;
END PROCESS;
DOUT5 <= QOUT5;
DOUT6 <= QOUT6;

-- L1: LED PORT MAP( DOUT1，LED1);
-- L2: LED PORT MAP( DOUT2，LED2);
-- L3: LED PORT MAP( DOUT3，LED3);
-- L4: LED PORT MAP( DOUT4，LED4);
-- L5: LED PORT MAP( DOUT5，LED5);
-- L6: LED PORT MAP( DOUT6，LED6);
END ARCHITECTURE CK;

下面是共阴数码管的程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY LED IS ------共阴管
PORT( QIN: STD_LOGIC_VECTOR(3 DOWNTO 0);
QOUT: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0));
END LED;

ARCHITECTURE DISPLAY OF LED IS
BEGIN
WITH QIN SELECT
QOUT <= "11111110" WHEN "0000"，
"01100000" WHEN "0001"，
"11011010" WHEN "0010"，
"11110010" WHEN "0011"，
"01100110" WHEN "0100"，
"10110110" WHEN "0101"，
"00111110" WHEN "0110"，
"11100000" WHEN "0111"，
"11111110" WHEN "1000"，
"11100110" WHEN "1001"，
"00000000" WHEN OTHERS;
END ARCHITECTURE DISPLAY;

这个是一个时钟程序；再加一个数码管显示就可以到数码管上显示出来了

这个电子钟是用六十进制和二十四进制写的

顶层文件：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CLOCK IS
PORT( CLK: IN STD_LOGIC;
CLR: IN STD_LOGIC;
RES: IN STD_LOGIC;
RES1 : IN STD_LOGIC_VECTOR( 5 DOWNTO 0); --秒钟重调
RES2 : IN STD_LOGIC_VECTOR( 5 DOWNTO 0); --分钟重调
RES3 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0); --时钟重调
QO1 : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0); -- 秒钟输出
QO2 : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0); --分钟输出
QO3 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0); --时钟输出
CO3 : OUT STD_LOGIC);
END ENTITY CLOCK;

ARCHITECTURE TIME OF CLOCK IS
SIGNAL CO1: STD_LOGIC;
SIGNAL CO2: STD_LOGIC;

COMPONENT COUNT60 IS
PORT ( CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
RES : IN STD_LOGIC;
QIN : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
QOUT : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0);
CO : OUT STD_LOGIC );
END COMPONENT;

COMPONENT COUNT24 IS
PORT ( CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
RES : IN STD_LOGIC;
QI : IN STD_LOGIC_VECTOR( 4 DOWNTO 0);
QO : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0);
CO : OUT STD_LOGIC );
END COMPONENT;
BEGIN

U1: COUNT60
PORT MAP( CLK，CLR，RES，RES1，QO1，CO1);
U2: COUNT60
PORT MAP( CO1，CLR，RES，RES2，QO2，CO2);
U3: COUNT24
PORT MAP( CO2，CLR，RES，RES3，QO3，CO3);
END ARCHITECTURE TIME;

下面是二十四进制计数

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNT24 IS
PORT ( CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
RES : IN STD_LOGIC;
QI : IN STD_LOGIC_VECTOR( 4 DOWNTO 0);
QO : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0);
CO : OUT STD_LOGIC );
END ENTITY COUNT24;

ARCHITECTURE BHV OF COUNT24 IS
SIGNAL Q : STD_LOGIC_VECTOR( 4 DOWNTO 0);
BEGIN
PROCESS( CLK， CLR， RES)
BEGIN
IF CLR = '1' THEN
Q <="00000";
ELSIF CLK'EVENT AND CLK='1' THEN
IF RES ='1' THEN
Q <=QI;
ELSIF Q = 23 THEN
Q <="00000";
CO <='1';
ELSE Q <= Q+1;
CO<='0';
END IF;
END IF;
END PROCESS;
QO <= Q;
END ARCHITECTURE BHV;
下面是六十进制计数

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNT60 IS
PORT ( CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
RES : IN STD_LOGIC;
QIN : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
QOUT : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0);
CO : OUT STD_LOGIC );
END ENTITY COUNT60;

ARCHITECTURE COUNT OF COUNT60 IS
SIGNAL Q : STD_LOGIC_VECTOR( 5 DOWNTO 0);

BEGIN
PROCESS (CLK，CLR，RES)
BEGIN
IF CLR = '1' THEN
Q <= "000000";
ELSIF CLK'EVENT AND CLK = '1' THEN
IF RES ='1' THEN
Q <= QIN;
ELSIF Q = 59 THEN
Q <= "000000";
CO <='1';
ELSE
Q <=Q + 1;
CO <= '0';
END IF;
END IF;
END PROCESS;
QOUT <= Q;
END ARCHITECTURE;

这个是用两个60进制和一个24进制做的

你只需要两个计数器ms，s。clock触发
process(clk) begin
if clk'event and clk='1' then
if ms=99 then ms<=0;
if s=59 then s<=0;
else s<=s+1; --秒进位
end if;
else ms<=ms+1; --毫秒进位
end if;
end if;
另外还需要一个七段译码器的程序，但是那个要根据管脚来写