跪求 基于verilog HDL设计的数字频率计数与模块的程序！超简单就行！

我自己写的.我测试好使.输出到二位动态数码管上，被测试频率由原来的clk产生，input，output写的很明白，能看懂吧?
module pinlvji(clk，clk_test，rst，out_wei，out_duan);
input clk，rst;
output [1:0]out_wei;
output [7:0]out_duan;
output clk_test;
reg [1:0]out_wei;
reg [7:0]out_duan=8'b00000011; //a b c d e f g dp
reg clk_test=0; // ce shi xin hao
reg [1:0] count1=2'b00;
reg [24:0] count2=0;
reg [18:0] count3=0;
reg [5:0] show; //largest 50M
reg [3:0] shi;
reg [3:0] ge;
reg flag=0; //yes or not get to one second
reg [19:0] saomiao;
reg [7:0] h;
reg [7:0] l;

always@(posedge clk) begin //creat a test signal 'clk_test'
if(count1==2'b11) begin // 50/8M
count1<=2'b00;
clk_test<=~clk_test;
end else
count1<=count1+1;
end

always@(posedge clk or negedge rst) begin //wait for 1 second ，then flag=1
if(!rst)
count2<=0;
else begin
if(!flag)
count2<=count2+1;
if(count2==25000000) begin // 1 second
flag<=1;
end
end
end

always@(posedge clk_test or negedge rst) begin //ji shu qi (1)
if(!rst)
count3<=0;
else if(!flag) begin
count3<=count3+1;
if(count3==500000) begin //1M
count3<=0;
show<=show+1;
end
end
end

always@(posedge clk) begin //scan
saomiao<=saomiao+1'b1;
if(!rst) begin
case(saomiao)
1 :begin
out_wei<=2'b10;
out_duan<=8'b00000011; //0
end
300000:begin
out_wei<=2'b01;
out_duan<=8'b00000011; //0
end
600000:saomiao<=0;
endcase
end
else begin
case(saomiao)
1 :begin
out_wei<=2'b10;
if(flag) out_duan<=l;
end
300000:begin
out_wei<=2'b01;
if(flag) out_duan<=h;
end
600000:saomiao<=0;
endcase
end
end

always@(posedge clk) begin
case(shi)
0:h=8'b00000011;
1:h=8'b10011111;
2:h=8'b00100101;
3:h=8'b00001101;
4:h=8'b10011001;
5:h=8'b01001001;
6:h=8'b11000001;
7:h=8'b00011111;
8:h=8'b00000001;
9:h=8'b00011001;
default:h=1'bx;
endcase
case(ge)
0:l=8'b00000011;
1:l=8'b10011111;
2:l=8'b00100101;
3:l=8'b00001101;
4:l=8'b10011001;
5:l=8'b01001001;
6:l=8'b11000001;
7:l=8'b00011111;
8:l=8'b00000001;
9:l=8'b00011001;
default:l=1'bx;
endcase
end

always@(posedge clk) begin //show
case(show)
0:begin shi=0;ge=0; end
1:begin shi=0;ge=1; end
2:begin shi=0;ge=2; end
3:begin shi=0;ge=3; end
4:begin shi=0;ge=4; end
5:begin shi=0;ge=5; end
6:begin shi=0;ge=6; end
7:begin shi=0;ge=7; end
8:begin shi=0;ge=8; end
9:begin shi=0;ge=9; end
10:begin shi=1;ge=0; end
11:begin shi=1;ge=1; end
12:begin shi=1;ge=2; end
13:begin shi=1;ge=3; end
14:begin shi=1;ge=4; end
15:begin shi=1;ge=5; end
16:begin shi=1;ge=6; end
17:begin shi=1;ge=7; end
18:begin shi=1;ge=8; end
19:begin shi=1;ge=9; end
20:begin shi=2;ge=0; end
21:begin shi=2;ge=1; end
22:begin shi=2;ge=2; end
23:begin shi=2;ge=3; end
24:begin shi=2;ge=4; end
25:begin shi=2;ge=5; end
26:begin shi=2;ge=6; end
27:begin shi=2;ge=7; end
28:begin shi=2;ge=8; end
29:begin shi=2;ge=9; end
30:begin shi=3;ge=0; end
31:begin shi=3;ge=1; end
32:begin shi=3;ge=2; end
33:begin shi=3;ge=3; end
34:begin shi=3;ge=4; end
35:begin shi=3;ge=5; end
36:begin shi=3;ge=6; end
37:begin shi=3;ge=7; end
38:begin shi=3;ge=8; end
39:begin shi=3;ge=9; end
40:begin shi=4;ge=0; end
41:begin shi=4;ge=1; end
42:begin shi=4;ge=2; end
43:begin shi=4;ge=3; end
44:begin shi=4;ge=4; end
45:begin shi=4;ge=5; end
46:begin shi=4;ge=6; end
47:begin shi=4;ge=7; end
48:begin shi=4;ge=8; end
49:begin shi=4;ge=9; end
50:begin shi=5;ge=0; end
51:begin shi=5;ge=1; end
default:begin shi=1'bx;ge=1'bx; end
endcase
end
endmodule

GOOGLE有类似问题的答案，你可以去看看