VHDL语言设计滤波器

只要用一个公式就行。library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fir is
Port (clk: in std_logic;
reset: in std_logic;
inpx: in std_logic_vector(11 downto 0);
outy: out std_logic_vector(11 downto 0));
end fir;
architecture beh of fir is
signal x0，x1，x2，x3: std_logic_vector(11 downto 0);
constant c0:integer :=-1234*32768/1000;
constant c1:integer :=2345*32768/10000;
constant c2:integer :=5*32768;
constant c3:integer :=-3*32768/10000;
signal p0，p1，p2，p3:integer;
signal sum: integer;
begin
sample_delay_line:
process(clk)
begin
if rising_edge(clk) then
if reset='1' then
x3 <=(others=>'0');
x2 <=(others=>'0');
x1 <=(others=>'0');
x0 <=(others=>'0');
else
x3 <=x2;
x2 <=x1;
x1 <=x0;
x0 <=inpx;
end if;
end if;
end process;
p0 <= conv_integer(x0)*c0;
p1 <= conv_integer(x1)*c1;
p2 <= conv_integer(x2)*c2;
p3 <= conv_integer(x3)*c3;
sum <=p0+p1+p2+p3;
outy <=conv_std_logic_vector(sum/32768，12);
end beh;